1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a semiconductor device for improving the reliability of a high-speed device employing a lifting structure of source/drain regions.
2. Description of the Prior Art
First and second conventional methods of fabricating field-effect transistors employing selective epitaxy for a lifting structure of source/drain regions are now described with reference to the drawings.
The first conventional method of fabricating a field-effect transistor is described with reference to FIGS. 45 to 51.
Referring to FIG. 45, element isolation films 2 are formed on a major surface of a silicon substrate 1 by trench isolation. The element isolation films 2 define an active region for forming a MOS (metal oxide semiconductor) transistor or the like on the surface of the silicon substrate 1. Thereafter a gate insulator film 3 is formed on the active region of the silicon substrate 1 by thermal oxidation.
A polysilicon film 4 and a silicon oxide film 5 are deposited on the major surface of the silicon substrate 1. Thereafter a photoresist film having a prescribed pattern is formed on the silicon oxide film 5 for thereafter anisotropically etching the polysilicon film 4 and the silicon oxide film 5 through the photoresist film serving as a mask and patterning the gate insulator film 3, the polysilicon film 4 and the silicon oxide film 5, for completing a gate electrode 6 consisting of the polysilicon film 4 and the silicon oxide film 5.
Referring to FIG. 46, an impurity is ion-implanted into the silicon substrate 1 through the gate electrode 6 serving as a mask, for forming n impurity regions 7a and 8a. Thereafter side walls 9 consisting of insulator films are formed on side surfaces of the gate electrode 6. Thereafter an impurity is ion-implanted into the silicon substrate 1 through the gate electrode 6 and the side walls 9 serving as masks, for forming n.sup.+ impurity regions 7b and 8b. Thus, a source region 7 and a drain region 8 are completed.
Referring to FIG. 47, epitaxial silicon layers 10 are formed on the source region 7 and the drain region 8 through selective epitaxy. Thereafter an impurity is introduced into the epitaxial silicon layers 10 by ion implantation.
Referring to FIG. 48, a metal thin film 22 of titanium is formed on the silicon substrate 1 by sputtering or the like. Referring to FIG. 49, the silicon substrate 1 is thereafter heat-treated at a high temperature for reacting the epitaxial silicon layers 10 with the metal thin film 22 and forming titanium silicide layers 23.
Referring to FIG. 50, the unreacted part of the metal thin film 22 is removed with sulfuric acid and hydrogen peroxide. No titanium silicide films 23 are formed on the side walls 9 provided with no epitaxial silicon layers 10. The gate electrode 6 is electrically isolated from the source region 7 and the drain region 8.
Referring to FIG. 51, an interlayer isolation film 14 is formed on the silicon substrate 1 by chemical vapor deposition or the like. Thereafter contact holes 14a are formed in the interlayer isolation film 14. Thereafter tungsten plugs 15 and aluminum wiring layers 16 are formed by a well-known technique, for completing a source electrode 18 and a drain electrode 19. A first field-effect transistor having the gate electrode 6, the source electrode 18 and the drain electrode 19 is completed through the aforementioned steps.
The second conventional method of fabricating a field-effect transistor is now described with reference to FIGS. 52 to 58.
Referring to FIG. 52, element isolation films 2 are formed on a major surface of a silicon substrate 1 by trench isolation. The element isolation films 2 define an active region for forming a MOS transistor or the like on the surface of the silicon substrate 1. Thereafter a gate insulator film 3 is formed on the active region of the silicon substrate 1 by thermal oxidation.
A polysilicon film is deposited on the major surface of the silicon substrate 1. Thereafter a photoresist film having a prescribed pattern is formed on the polysilicon film for thereafter anisotropically etching the gate insulator film 3 and the polysilicon film through the photoresist film serving as a mask and patterning the polysilicon film, for completing a gate electrode 6 consisting of the polysilicon film.
Referring to FIG. 53, an impurity is thereafter ion-implanted into the silicon substrate 1 through the gate electrode 6 serving as a mask, for forming n.sup.- impurity regions 7a and 8a. Thereafter side walls 9 consisting of insulator films are formed on side surfaces of the gate electrode 6. Thereafter an impurity is ion-implanted into the silicon substrate 1 through the gate electrode 6 and the side walls 9 serving as masks, for forming n.sup.+ impurity regions 7b and 8b. Thus, a source region 7 and a drain region 8 are completed.
Referring to FIG. 54, epitaxial silicon layers 10 are formed on the source region 7 and the drain region 8 through selective epitaxy. At this time, an epitaxial silicon layer 10 is formed also on the gate electrode 6. Thereafter an impurity is introduced into the epitaxial silicon layers 10 by ion implantation.
Referring to FIG. 55, a metal thin film 22 of titanium is formed on the silicon substrate 1 by sputtering or the like. Referring to FIG. 56, the silicon substrate 1 is thereafter heat-treated at a high temperature for reacting the epitaxial silicon layers 10 with the metal thin film 22 and forming titanium silicide layers 23. A titanium silicide layer 23 is formed also on the epitaxial silicon layer 10 formed on the gate electrode 6.
Referring to FIG. 57, the unreacted part of the metal thin film 22 is removed with sulfuric acid and hydrogen peroxide. No titanium silicide layers 23 are formed on the side walls 8 provided with no epitaxial silicon layers 10. The gate electrode 6 is electrically isolated from the source region 7 and the drain region 8.
Referring to FIG. 58, an interlayer isolation film 14 is formed on the silicon substrate 1 by chemical vapor deposition or the like. Thereafter contact holes 14a are formed in the interlayer isolation film 14. Thereafter tungsten plugs 15 and aluminum wiring layers 16 are formed by a well-known technique, for completing a source electrode 18 and a drain electrode 19. A second field-effect transistor having the gate electrode 6, the source electrode 18 and the drain electrode 19 is completed through the aforementioned steps.
The aforementioned two conventional methods of fabricating field-effect transistors through selective epitaxy have the following problems:
In the first conventional method of fabricating a field-effect transistor, the epitaxial silicon layers 10 are formed only on the source region 7 and the drain region 8, as shown in FIG. 47. Literature "Journal of Crystal Growth 111" (1991), pp. 860 to 863 reports that silicon fragments of such epitaxial silicon layers 10 are formed on the side walls 9 when the thickness of the epitaxial silicon layers 10 exceeds a certain value in formation thereof.
This literature describes that material gas of disilane, for example, colliding with a surface of the silicon oxide film 5 during the growth process of the epitaxial silicon layers 10 is partially decomposed to form movable adatoms on the surface of the silicon oxide film 5.
When the surface of the silicon oxide film 5 is covered with the adatoms in a certain ratio, polysilicon grows from the adatoms serving as nuclei. The growing polysilicon forms the silicon fragments. When the side walls 9 are formed by silicon nitride films, further, the limit thickness for preventing such formation of the silicon fragments is reduced.
When forming the epitaxial silicon layers 10 in a thickness of 20 nm under a silicon substrate temperature of 680.degree. C. and a disilane flow rate of 0.2 sccm, for example, the deposition time is about four minutes. At this time, silicon fragments of polysilicon having a thickness of about 4 nm are formed on the side walls 9 of silicon nitride films.
When the silicon fragments are formed on upper surfaces of the side walls 9, the source electrode 18 and the drain electrode 19 may be shorted through the silicon fragments.
Particularly when the metal thin film 22 is formed by sputtering after formation of the epitaxial silicon layers 10 to be reacted with the epitaxial silicon layers 10 by high-temperature heat treatment for forming the titanium silicide layers 23 as described with reference to FIG. 48, the silicon fragments react with the metal thin film 22 to form unnecessary titanium silicide layers 23a, as shown in FIG. 59.
After the unreacted part of the metal thin film 22 is removed with sulfuric acid and hydrogen peroxide or the like, the unnecessary silicide layers 23a remain on the side walls 9. Thus, the source electrode 18 and the drain electrode 19 are disadvantageously shorted due to the presence of a smaller amount of unnecessary titanium silicide layers 23a remaining on the side walls 9.
Also in the second conventional method of fabricating a field-effect transistor, the gate electrode 6 is disadvantageously shorted with the source electrode 18 and the drain electrode 19 due to unnecessary titanium silicide layers 23a formed on the side walls 9 when the titanium silicide layer 23 is also formed on the epitaxial silicon layer 22 growing on the gate electrode 6, as shown in FIG. 60.